1. Field of the Invention
The present invention pertains to a PWM power amplifier, and more specifically to a digital input PWM power amplifier.
2. Description of the Related Art
The general trend to reduce energy consumption and the weight and overall dimension represented by heatsinks has stimulated the request of equipment manufacturers for audio power amplifiers with greater efficiency than xe2x80x9cABxe2x80x9d class amplifiers.
To meet these requests audio amplifiers in class D have been proposed which comprises a DC-AC converter circuit which produces a pulse width modulated (PWM) output signal; said PWM signal in turn drives power switches which drive a load provided with a passive filter for the reconstruction of the amplified audio signal.
A single output amplifier with analogue input and PWM output (class-D amplifier) is described in the article xe2x80x9cAnalysis of a quality class-D amplifier,xe2x80x9d F.A. Himmelstoss, et al., I.E.E.E. Transactions on Consumer Electronics, Vol. 42, No. 3, August 1996.
Widening interest in the digital processing of signals has lead to the manufacture of power amplifiers with digital input instead of analogue input. Digital input power amplifiers include PCM/PWM converters capable of converting a pulse code modulation (PCM) digital signal into a PWM digital signal, and a final stage of power amplification receiving the PWM digital signal and generating an amplified PWM analogue output signal that drives a load provided with a passive filter for the reconstruction of the amplified audio signal. The PCM/PWM converter comprises a counter fed by a clock signal and generating digital comparison words and a digital comparator receiving the digital comparison words through a first input and the PCM digital signal through a second input and producing a digital PWM signal in output.
In a power amplifier of the above type, the device for generating the clock signal needed for the PCM/PWM conversion of the digital signal in input is typically made up of a PLL clock generator (phase locked) which, in per se known way, consists of a loop structure comprising a phase comparator, a filter, a voltage controlled oscillator, and a frequency divider.
A PLL clock generator nevertheless presents a complex structure and is affected by various types of noise above all in virtue of the presence of the phase comparator.
In view of the state of the technique described, the present invention provides a PWM power amplifier provided with a clock generator that at least partially eliminates the above mentioned inconveniences.
In accordance with the disclosed embodiments of the present invention, a PWM power amplifier is provided that has at least one PCM/PWM converter that is fed with PCM digital input signals and produces PWM digital output signals, and at least one final stage of power amplification of the PWM digital signals in output from the at least one PCM/PWM converter. The at least one PCM/PWM converter includes a counter fed with at least one clock signal produced by a clock generator device and having a digital comparator suitable for comparing the PCM digital input signals of the at least one PCM/PWM converter with a digital comparison signal produced by the counter and producing the PWM digital signals in output. The clock generator device includes a pulse generator device and an oscillator, the pulse generator device receiving a signal at a frequency that is equal to the frequency of the PCM digital input signals of the at least one PCM/PWM converter and producing reset pulses in output, the reset pulses being sent in input to the oscillator producing the at least one clock signal in output.
Because of the present invention a PWM power amplifier can be produced that is provided with a clock generator having a simpler circuit than the known clock generator devices and that is less effected by noise in comparison with the same known devices.